The present invention is related to CMOS Static Random Access Memory (SRAM) devices, and more particularly, to an SRAM cell having P channel field-effect transistors a s passgate devices to significantly reduce the surface area of all the transistors forming the cell, to improve the cell stability, and to lower the power dissipated by the cell.
Conventional CMOS SRAM cells typically consist of six transistors: two P channel field effect transistors (PFETs) for a pull-up operation, two N channel field effect transistors (NFETs) for pull down, and two NFETs for input/output (i.e., passgate) access. As shown in FIG. 1A, P1 and N1 form an inverter which is cross-coupled with another inverter consisting of P2 and N2. NL and NR are the passgate access devices which control reading from and writing into the cell. The corresponding layout for the above circuit is shown in FIG. 1B. The two pull-up PFETs P1 and P2 are referenced by numeral 102, the two pull down NFETs N1 and N2 by 111, and the passgate NFETs NL and NR by 101. For simplicity sake, metal shapes are not shown. In the particular layout, the word line (WL) is shown at first level metal M1 along the X-direction. The bit lines and the GND line are represented at the second level metal M2 along the Y-direction. Line 121 is the left bit line BL; line 122, the right bit line BR; and line 120, the vertical GND bus. The shape referenced by RX represents the active silicon area; PC, the polysilicon; CA, the contact from the first level metal M1 to PC or RX; and NW, the region for the N-well of the P-channel devices.
A conventional SRAM array consists of m rows and n columns of the aforementioned SRAM cells. Cells of the same row share one WL, while cells of the same column share the same bit line pair, consisting of BL and BR. The aforementioned design is used in many SRAMs, including, e.g., 1 Mega-bit memory having, typically, 1024 by 1024 cells.
During standby, all the WLs are at low (i.e., at GND level) and all bit lines are biased to the standby voltage level (of the power supply) Vdd. Thus, the NFET passgate devices NL and NR of all the cells are shut off. A data bit 1 is maintained with P1 and N2 on, and P2 and N1 off, such that the left cell node CL is at high (i.e., Vdd) while CR is at low (GND). Correspondingly, a data bit 0 is maintained when P2 and N1 are on, and P1 and N2 off, which forces the right cell node CR to high (i.e., Vdd) and the left node CL to GND. During access time, one WL is selected by being switched on (to Vdd) such that half of the PFET passgate devices along the selected WL are turned on simultaneously. For each cell along the selected WL, one passgate device is turned on.
During a read access operation, either BL or BR are pulled down from their high (at Vdd) by the cell. BL is pulled down if the cell is at 0, whereas BR is pulled down if the cell is at 1. A bit select multiplexor then steers the selected bit pair(s) to appropriate sense amplifiers to generate the digital signals for the external circuitry requesting the read memory operation. The sense signals developed along the unselected bit columns are ignored. The cells along the selected WL that were not selected are referred to as the xe2x80x98half-selectedxe2x80x99 cells.
During a write access operation, the bit select circuitry steers the input data into the selected bit pairs. To write a 1, BL is driven to high (i.e., to Vdd) and BR to low (i.e., to GND), shutting off N1 and P2, while turning on N2 and P1. To write a 0, BL is forced to low and BR to high. Along the unselected bit columns, BL and BR are coupled to Vdd and are gradually pulled down by the xe2x80x98half-selectedxe2x80x99 cells, as previously described in the read operation. Thus, during a read access operation, all the cells along the selected WL are disturbed since one NFET passgate device of each SRAM cell remains on. During a write access, all the xe2x80x98half-selectedxe2x80x99 cells are similarly disturbed as during the read operation. When a cell is at 0, the left cell node CL is at GND. When WL is raised to high (i.e., Vdd), the passgate device NL switches on, raising BL to Vdd and pulling the left cell node up. Thus, NL and N1 act as a potential divider at CL between Vdd and GND. To prevent the node CL from rising beyond the threshold voltage of N2, the conductance of N1 must be larger than the conductance of NL. Otherwise, N2 turns on, pulling down the node CR, switching P1 on, and raising the node CL from GND to Vdd. In such an instance, the cell is disturbed from its 0 state to a 1 state.
Thus, the ratio of the conductance of N1 over the conductance of NL is a basic metric to measure the stability of the SRAM. This ratio is referred to by CMOS SRAM designers as xe2x80x98betaxe2x80x99 or xe2x80x98beta ratioxe2x80x99. It is defined as the ratio of the conductance of the pull down device 111 over the conductance of passgate device 101.
There is no precise analytical expression for the conductance of the transistors. It is approximately proportional to m (pw/pl), wherein pl is the device channel length; pw, the device channel width and m, the effective carrier mobility. Accordingly, the beta of the cell can be approximated by the ratio of (m*pw/pl) of transistor N1 and (m*pw/pl) of NL. If N1 and NL have the same channel length, then the beta ratio becomes the ratio of the channel width of N1 over the channel width of NL. Referring back to FIG. 1B, the channel width of N1 is 0.36 xcexcm, and the channel width of NL, 0.18 xcexcm. Thus, the beta ratio equals 2. Depending on the SRAM application, beta ranges from 1.8 to 3. In general, beta needs to be bigger for faster operations.
Referring back to FIG. 1A, the six-transistor (6-T) cell shown therein has typically been the basic structure used in SRAM circuit designs, even though it is much larger than, e.g., a 1-T DRAM. Indeed, the cell size ratio between SRAM and DRAM generally exceeds 8. Many attempts have been made in the past to reduce the size of the SRAM cell. However, these attempts are routinely achieved by trade-offs between certain desirable feature characteristics of the 6-T SRAM cell. By way of example, in an article entitled xe2x80x9cA 2.9 xcexcm2 Embedded SRAM Cell with Co-salicide Direct-Strap Technology for 0.18 xcexcm High Performance CMOS Logicxe2x80x9d, published in IEDM 97, pp 847-850, the cell size is reduced by removing the pull-up P channel FETs. This replacement introduces significant problems when the cell stability degrades and standby power dissipation increases. A cell read operation becomes destructive, and write back provisions must be introduced. As a result, the cycle time increases significantly and the access power becomes unacceptably large. Further, a standby pull-up current must also be provided to retain the cell data. Thus, the standby power becomes very significant.
In a second example, in U.S. Pat. No. 5,747,979, xe2x80x9cHigh Density SRAM Circuitxe2x80x9d, issued Sep. 10, 1991, the pull-down NFET device is reduced to the same minimum size of the passgate device, without changing the NFET passgate device to a PFET passgate device. The area saving approaches those of the present invention. However, this reduction is attained at the expense of the cell beta degrading from 2 to 1. Thus, an array write back must be provided after every access, and no bit selection is possible. The cycle time needs to be stretched out and a considerable amount of extra power must be provided. Finally, the cells are still susceptible to disturbs, wherein the cells may have already flipped over before the sense signal is established for the subsequent write back. To minimize disturbing the less stable cells, data write back is provided after each access operation, as was required in the previous reference In another reference, U.S. Pat. No. 6,044,010, xe2x80x9cFive Device SRAM Cellxe2x80x9d, issued Mar. 28, 2000, the cell size is reduced by removing one of the two passgate transfer devices. By doing so, the read operation is slowed down for lack of bit pair sensing. Writing is also difficult. Finally, the NFET passgate transfer device must be very large to overcome the internal N channel FET pull down when writing a 1. The cell size ends up being even larger to save one bit line wiring channel. The size of the passgate transfer device remaining in the 5-T SRAM cell can be reduced if the write operation consists of a preset step followed by a reset step. Then, the write time will be twice as long and a column deselect will still not be possible.
In U.S. Pat. No. 6,030,548, xe2x80x9cSRAM Memory Device Having Reduced Sizexe2x80x9d, issued Feb. 29, 2000, the cell size is reduced by introducing an extra layer of polysilicon runner to serve as the word line. The problems introduced are the extra cost of the more complicated process, and the inherent larger RC delays of the polysilicon wiring.
Besides the SRAM cell size, other considerations such as stability and power dissipation problems are emerging, as a result of technology down scaling. As the cells shrink in size, the cells are more prone to flipping because of cosmic rays and alpha particles. Accordingly, soft errors have dramatically increased with every new generation. Further, the off currents of the FET devices also increase exponentially because of the shortened channels. Thus, the SRAM cells become too hot and too unstable as the technology continues its scaling down progression by reducing the size of the cell with more advanced lithography and fabrication processes.
Accordingly, it is a primary object of the invention to provide an SRAM cell that is significantly cooler, more stable, and smaller in size, while still remaining within the technology design ground rules constraints, and without adding any additional process steps.
It is another object to replace the NFET passgate devices with PFET devices and guarantee an electrical conductivity ratio of 2 even though the physical channel size ratio is reduced to 1.
It is yet another object to provide an SRAM cell wherein the transistors forming the cell have a minimum size with no degradation of the cell stability.
It is still another object to significantly improve cell stability and reduce power dissipation.
It is a further object to significantly reduce the size of a dual-port SRAM cell, wherein one pair of passgate devices are PFETs and the other, NFETs, and still maintain high stability and low power dissipation associated with the PFET passgate devices.
It is yet a further object to minimize the size of the multi-port SRAM cell, wherein one-half of the passgate pairs are PFETs, and the remaining passgate device pairs are NFETs and still maintain higher stability and lower power dissipation associated with the PFET passgate devices.
These and other objects of the invention are achieved by an SRAM cell wherein by introducing PFET passgate devices, it is possible to reduce the total surface area of the pull-up and pull-down devices. In a first embodiment of invention, a 6-T, single-port SRAM cell dissipates less power than conventional devices by over 75%, the cell stability is improved by more than 2 times ,and the total cell size is reduced by at least 10%. The overall cell is significantly smaller since all the six transistors take minimum dimensions. The power saving is the result of a differential sensing made possible by the PFET passgate devices, by the smaller standby off-current of the smaller devices and by the smaller loading of the shorter bit lines. The cell stability is also improved by having the current leakage margin increased to 40 xcexca from a conventional current leakage margin of 10 xcexca.
In a second aspect of the invention, an eight-transistor (8-T), dual-port cell, the more balanced proportion of 4 PFETs and 4 NFETs of the cell allows a surface area saving of 50%, over a conventional layout of 2 PFETs and 6 NFETs. Power saving and stability improvement are also achieved with the PFET port. Disturbs through the NFET port remain the same as in conventional designs.
All these advantages are achieved while remaining within the same technology ground rule constraints, using the same basic process steps and layout ground rules.
Accordingly, there is provided a single-port SRAM cell formed by a first pair of P channel field effect transistors (PFET), each of the PFETs having a common source connected to a voltage potential and a gate connected to a drain of the other PFET; a pair of N channel field effect transistors (NFET), each of the NFETs having a drain connected to the drain of the respective PFET of the first pair of PFETs, a common source connected to ground, and a gate connected to the drain of an opposite PFET of the first pair of PFETs; a second pair of PFETs having the drain respectively connected to the connection linking the respective drain of the NFET of the pair of NFETs to the drain of the PFET of the first pair of PFETs;complementary bit lines, each of the bit lines respectively connected to the source of the PFET of the second pair of PFETs; and a word line connected to the gates of the PFETs of the second pair of PFETs.
It is further provided a dual-port SRAM cell formed by a first pair of PFETs, each of the PFETs having a common source connected to a voltage potential and a gate connected to a drain of the other PFET; a first pair of NFETs, each of the NFETs having a drain connected to the drain of the first pair of PFETs, a common source connected to ground and having a gate connected to the drain of an opposite PFET; a second pair of PFETs having a drain respectively connected to the connection linking the respective drain of the NFET of the first pair of NFETs and to the drain of the PFET of the first pair of PFETs; a second pair of NFETs having a drain respectively connected to the connection linking the respective drain of the PFET of the first pair of PFETs and to the drain of the NFET of the first pair of NFETs; a first pair of complementary bit lines respectively connected to a source of the PFET of the second pair of PFETs; a second pair of complementary bit lines respectively connected to a source of the NFET of the second pair of NFETs; a first word line connected to the gates of the PFETs of the second pair of PFETs; and a second word line connected to the gates of the NFETs of the second pair of NFETs.